This invention relates to the manufacture of semiconductor devices. More particularly, the invention relates to an improved method for fabricating FET devices when both NFET and PFET devices are to be integrated in the same circuit, for example in high performance CMOS logic circuits.
Fabrication of integrated circuits generally involves integration of FET devices. Many high performance circuit designs in the present state of the art include both NFET and PFET devices. A conventional FET fabrication process includes building a gate structure 10 on a substrate (generally a silicon wafer) 1, and using an ion implant process to form source and drain regions 2, 3 (see FIG. 1A). In particular, as shown schematically in FIG. 1A, an ion implant 12 may be used with a blockout mask 11 to form shallow extension regions 4, 5 close to the gate structure. An angled ion implant, where the ions are incident on the substrate at an angle other than 90 degrees, may be used to form extension regions of the source and drain under the gate structure.
In a conventional integration scheme involving the fabrication of both PFET and NFET devices, the extension regions 4, 5 of the NFET are implanted with no sidewall spacer present, as shown in FIG. 1A. A typical addition to this scheme employs a thermal oxidation process (also called reoxidation) to offset the extension regions 4, 5 of the NFET from the edge of the gate structure 10 (see FIG. 1B). The thickness of the reoxidation layer 15 is less than 10 nm, and typically less than about 5 nm.
In order to obtain greater flexibility in device design, sidewall spacers 13 are often formed on the sides of the gate structure 10, to control the spacing of the extensions with respect to the gate (see FIG. 1C); the thickness of the sidewall spacer defines the offset distance for the extension. As shown schematically in FIG. 1C, an ion implant 14 is used with a blockout mask 16 to form the PFET extensions 6, 7 after the sidewall spacers 13 are formed.
Since the spacer 13 is formed on the sidewalls of the gate structure in both NFET and PFET devices, the NFET is subjected to the various spacer processing steps (including spacer deposition, spacer etch and polymer clean) after the NFET extension implant 12. When a reoxidation process is used, a significant portion of the NFET extension ion implant dose remains in the oxide layer; the extension implant is thus divided into portions 4a, 5a in the oxide and very shallow portions 4b, 5b in the substrate. To avoid etching into portions 4b, 5b in the substrate, a spacer etch process is required which is highly selective to the reoxidation. This situation becomes more acute as CMOS devices are scaled so that the reoxidation layer 15 becomes thinner. Loss of the NFET extension implant dose during spacer etch leads to higher extension resistance, which in turn reduces the drive current for the NFET device. (The NFET extension implant process is typically performed using arsenic ions; the spacer formation process has been found to remove about 30% of the As dose.) The potential overetch of the substrate (with resulting extension dose loss) also varies from wafer to wafer; causing unacceptable variations in device parametrics.
Furthermore, if the spacer material is silicon nitride, a polymer clean process is required after the etch process to define the sidewall spacers. The polymer clean is performed by exposing the entire wafer to a residual polymer removal process which results in the growth of oxide on the surface. The oxide layer thus formed may be as much as 6.5 nm thick; accordingly, about 3.0 nm of the Si substrate is consumed as the oxide is formed. This process further reduces the thickness of implanted portions 4b, 5b in the NFET extension. The oxide growth also has undesirable effects on the PFET devices. To obtain very shallow p-type extensions 6, 7 in the PFET, a desirable implant 14 includes a dose of low-energy boron or BF2 ions. The oxide growth prevents the use of low-energy boron or BF2 since the low-energy ions tend to stop in the oxide instead of in the substrate.
There is a need for an improved spacer formation process that permits formation of a shallow PFET extension with the spacer present while avoiding degradation of the implanted NFET device.
The present invention addresses the above-described need by providing a method for making a semiconductor device which includes a gate structure on a substrate, and elevated sidewall spacers on the gate structure. In accordance with the invention, a method is provided for producing an NFET device, within the context of a CMOS process flow, having improved source/drain extension characteristics by increasing retention of the extension ion implant dose and reducing dose variation from wafer to wafer. A method is also provided for producing a PFET device having ultra-shallow junction extension implants, also within the context of a CMOS process flow.
The elevated sidewall spacers of the present invention are constructed as follows: After gate stack patterning, a first layer is deposited on the substrate. Reoxidation may also be performed before the first layer is deposited. A top portion of the first layer is then removed, so that an upper portion of each of the sidewalls extends above a remaining portion of the first layer. A second layer is deposited on the remaining portion of the first layer and on the gate structure. Portions of the second layer-those disposed on the remaining portion of the first layer and on the top surface of the gate structure-are removed, so that a remaining portion of the second layer is disposed on the upper portion of each of the sidewalls. The remaining portion of the first layer is then removed, so that the remaining portion of the second layer on each of the sidewalls projects laterally therefrom and is elevated with respect to the substrate. The first layer is preferably either self-planarizing or is subjected to a planarization process. The second layer is preferably deposited in a conformal deposition process, so that the second layer is deposited on the top surface and on the sidewalls of the gate structure. The step of removing portions of the second layer preferably comprises a directional etching process; the final step of removing the remaining portion of the first layer preferably comprises a non-directional etching process. The first layer and the second layer may be formed of insulating materials. The remaining portion of the second layer, which forms an elevated spacer, projects from the sidewall by a distance in accordance with the thickness of the deposited second layer.
After the elevated sidewall spacer has been formed, a lithography step may be used to block the PFET regions. Next, an ion implantation process is used to implant the NFET extension at an angle such that the ions are not blocked by the elevated spacer. An additional ion implantation process may be performed at normal incidence to the surface for the NFET extension. The elevated spacer structure of the present invention thus permits a double NFET extension implant, thereby reducing the resistance in the extension and improving device performance. A lithography step may be used to provide a blockout mask covering the NFET device while the PFET device is exposed. The PFET extension is then implanted at normal incidence with respect to the surface, so that the elevated spacer provides an offset of the implant with respect to the edge of the gate structure. An additional, angled, ion implant process may then be done for the PFET extension.
The CMOS devices (NFET and PFET) fabricated according to this method avoid the drawbacks encountered in conventional processing. Specifically, the NFET device does not suffer from ion implant dose loss caused by the PFET spacer etch process. Source and drain extensions for both devices may be implanted using very low energy ion implant processes, because no oxide film is present on the horizontal substrate surface. In addition, the method of the present invention permits ion implant processes for both the NFET and PFET to be performed at multiple incidence angles.
According to another aspect of the invention, a semiconductor device is provided which includes a gate structure disposed on a substrate. The gate structure has a top surface and a sidewall, and a spacer is disposed on the sidewall and projects laterally therefrom. The spacer covers an upper portion of the sidewall and is elevated with respect to the substrate. The spacer may extend along the sidewall from the top surface to a point above a surface of the substrate. The spacer is preferably formed of an insulating material, and may project laterally from the sidewall by a distance determined by a thickness of a layer deposited on the top surface and sidewall of the gate structure.